Semiconductor package and method of manufacturing the same

A semiconductor package, comprising:

• a lower redistribution structure including
• a lower redistribution insulation layer,
• a bump pad in the lower redistribution insulation layer, and
• a lower redistribution pattern electrically connected to the bump pad,
• wherein the lower redistribution insulation layer includes one or more sidewalls at least partially defining a cavity extending from a bottom surface of the lower redistribution insulation layer to an upper surface of the lower redistribution insulation layer;
• a passive component in the cavity of the lower redistribution insulation layer;
• an insulation filler in the cavity of the lower redistribution insulation layer, the insulation filler covering sidewalls of the passive component;
• a semiconductor chip on the lower redistribution structure, the semiconductor chip electrically connected to both the lower redistribution pattern and the passive component;
• and
• an external connection bump connected to the bump pad through a pad opening of the lower redistribution insulation layer, the external connection bump connected to the bottom surface of the lower redistribution insulation layer,
• wherein a surface roughness of the bottom surface of the lower redistribution insulation layer is greater than a surface roughness of the upper surface of the lower redistribution insulation layer.

A semiconductor package, comprising:

• a lower package and an upper package stacked on the lower package,
• wherein the lower package includes
• a lower redistribution structure that includes
• a lower redistribution insulation layer,
• a bump pad in the lower redistribution insulation layer, and
• a lower redistribution pattern electrically connected to the bump pad,
• wherein the lower redistribution insulation layer includes one or more sidewalls at least partially defining a cavity extending from a bottom surface of the lower redistribution insulation layer to an upper surface of the lower redistribution insulation layer;
• a passive component in the cavity of the lower redistribution insulation layer;
• an insulation filler in the cavity of the lower redistribution insulation layer, the insulation filler covering sidewalls of the passive component;
• a first semiconductor chip on the lower redistribution structure, the first semiconductor chip electrically connected to both the lower redistribution pattern and the passive component;
• a chip connection bump between the lower redistribution structure and a first chip pad of the first semiconductor chip;
• a conductive connection pillar attached to a connection pad of the passive component;
• a component connection bump between the conductive connection pillar and a second chip pad of the first semiconductor chip;
• a molding layer on the lower redistribution structure, the molding layer covering the first semiconductor chip;
• a conductive post penetrating the molding layer, the conductive post electrically connected to the lower redistribution pattern;
• an upper redistribution structure on the molding layer, the upper redistribution structure including
• an upper redistribution insulation layer, and
• an upper redistribution pattern electrically connected to the conductive post;
• and
• an external connection bump connected to the bump pad through a pad opening of the lower redistribution insulation layer, the external connection bump connected to the bottom surface of the lower redistribution insulation layer,
• wherein the upper package includes
• a package substrate stacked on the upper redistribution structure via an inter-package connection terminal, and
• a second semiconductor chip on the package substrate,
• wherein the insulation filler includes a bottom surface exposed to an exterior of the semiconductor package through the bottom surface of the lower redistribution insulation layer, and
• wherein a surface roughness of the bottom surface of the lower redistribution insulation layer is greater than both a surface roughness of the bottom surface of the insulation filler and a surface roughness of the upper surface of the lower redistribution insulation layer.