Package substrate and semiconductor package including the same

A semiconductor package comprising:

• a package substrate including a base having a front side and an opposite back side, front pads on the front side of the base, a support pattern on the front side of the base having a thickness greater than a thickness of each of the front pads, and a protective insulating layer on the front side of the base and having openings exposing the front pads, respectively, and in contact with at least a portion of the support pattern;
• a lower semiconductor chip on the protective insulating layer and spaced apart from the support pattern in a horizontal direction;
• and
• a first upper semiconductor chip vertically overlapping the lower semiconductor chip and the support pattern, on the protective insulating layer and the lower semiconductor chip, wherein the support pattern includes a metal post, and
• a lower surface of the support pattern is below upper surfaces of the front pads.

A package substrate comprising:

• a base having a front side an opposing back side;
• rear pads below the back side of the base;
• front pads on the front side of the base;
• support patterns on the front side of the base and having a thickness greater than a thickness of each of the front pads;
• and
• a protective insulating layer on an upper surface and a side surface of each of the support patterns on the front side of the base and having openings exposing the front pads respectively,
• wherein the base includes a plurality of base insulating layers and an interconnection structure extending through the plurality of base insulating layers and electrically connecting the front pads and the rear pads.