Semiconductor memory device and method of fabricating the same

A semiconductor memory device, comprising:

• a semiconductor substrate that includes a cell array region and a peripheral region;
• a plurality of bottom electrodes on the semiconductor substrate on the cell array region;
• a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes;
• and
• a top electrode on the dielectric layer and between the bottom electrodes,
• wherein the top electrode includes a first metal layer, a silicon-germanium layer, a conductive adhesion layer, a second metal layer, and a silicon layer that are sequentially stacked.

A semiconductor memory device, comprising:

• a semiconductor substrate that includes a cell array region and a peripheral region;
• a word line in the semiconductor substrate on the cell array region;
• a first impurity region in the semiconductor substrate on one side of the word line;
• a second impurity region in the semiconductor substrate on another side of the word line;
• a bit line disposed on the semiconductor substrate on the cell array region and connected to the first impurity region, the bit line crossing over the word line;
• a bottom electrode disposed on the semiconductor substrate on the cell array region and connected to the second impurity region;
• a dielectric layer that conformally covers a sidewall and a top surface of the bottom electrode;
• and
• a top electrode on the dielectric layer,
• wherein the top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked,
• wherein a surface roughness at a top surface of the silicon layer is equal to or less than about 10 nm root mean square (RMS), and
• wherein a surface roughness at a lateral surface of the silicon layer is greater than about 10 nm root mean square (RMS) and equal to or less than about 1,000 nm root mean square (RMS).