Multi-chip assembly and methods of producing multi-chip assemblies

A method of producing multi-chip assemblies, the method comprising:

• processing a semiconductor wafer into a plurality of separated dies, the plurality of separated dies including a first group of separated dies and a second group of separated dies;
• and
• via wafer-level processing:
• replacing the second group of separated dies with a third group of separated dies;
• securing the separated dies of the first group and the third group to one another with a dielectric material;
• electrically interconnecting groups of two or more adjacent ones of the separated dies from the first group and the third group;
• and
• removing the dielectric material in a region between the groups of electrically interconnected dies to laterally separate the groups of electrically interconnected dies from one another.

A multi-chip assembly, comprising:

• a first power transistor die having a source terminal facing a first direction, and a drain terminal facing a second direction opposite the first direction;
• a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction;
• a dielectric material occupying a gap between the first power transistor die and the second power transistor die, and securing the first power transistor die and the second power transistor die to one another;
• and
• a metallization connecting the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly,
• wherein the gap occupied by the dielectric material is less than 70 μm.