US 2023/0145678 A1Published application

Semiconductor memory device and manufacturing method of semiconductor memory device

AssigneeUnisantis Electronics Singapore Pte. Ltd.

InventorsRiichiro SHIROTA, Nozomu HARADA, Koji SAKUI, Masakazu KAKUMU

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Abstract

A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.

Claims20

Dependent claims

A manufacturing method of a semiconductor memory device that performs a data retention operation and a data erase operation, the data retention operation being an operation in which voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity layer, and a second impurity layer are controlled to retain, inside a semiconductor pillar, a group of holes or electrons that are generated by an impact ionization phenomenon or a gate induced drain leakage current and that serve as majority carriers in the semiconductor pillar, and the data erase operation being an operation in which the voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer are controlled to remove, from the semiconductor pillar, the group of holes or electrons that serve as majority carriers in the semiconductor pillar, the manufacturing method comprising:

a step of stacking, on a substrate, from a bottom in a vertical direction, the first impurity layer, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer;
a step of forming a first hole whose bottom portion is on an upper surface or in an inside of the first impurity layer and that penetrates the first insulating layer, the first material layer, the second insulating layer, the second material layer, the third insulating layer, the third material layer, and the fourth material layer;
a step of forming the semiconductor pillar to be embedded in the first hole;
a step of removing the first material layer to form a second hole, removing the second material layer to form a third hole, and removing the third material layer to form a fourth hole;
a step of oxidizing an outermost surface of the semiconductor pillar exposed in the second hole to form a first gate insulating layer, oxidizing an outermost surface of the semiconductor pillar exposed in the third hole to form a second gate insulating layer, and oxidizing an outermost surface of the semiconductor pillar exposed in the fourth hole to form a third gate insulating layer;
a step of forming the first gate conductor layer embedded in the second hole and covering the first gate insulating layer, forming the second gate conductor layer embedded in the third hole and covering the second gate insulating layer, and forming the third gate conductor layer embedded in the fourth hole and covering the third gate insulating layer;
and
a step of forming the second impurity layer connected to a top portion of the semiconductor pillar.

5 more elements

A semiconductor memory device comprising:

a semiconductor base on a substrate, the semiconductor base standing vertically or extending horizontally to the substrate;
a first impurity layer and a second impurity layer at both ends of the semiconductor base;
a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer surrounding part or all of a side surface of the semiconductor base between the first impurity layer and the second impurity layer sequentially from the first impurity layer toward the second impurity layer, the first gate insulating layer being in contact with or in proximity to the first impurity layer, the second gate insulating layer surrounding part or all of the side surface of the semiconductor base and being connected to the first gate insulating layer, and the third gate insulating layer surrounding part or all of the side surface of the semiconductor base, being connected to the second gate insulating layer, and being in contact with or in proximity to the second impurity layer;
a first gate conductor layer covering the first gate insulating layer;
a second gate conductor layer covering the second gate insulating layer;
a third gate conductor layer covering the third gate insulating layer;
a second insulating layer between the first gate conductor layer and the second gate conductor layer;
and
a third insulating layer between the second gate conductor layer and the third gate conductor layer, wherein
the semiconductor memory device performs a memory write operation by performing an operation in which voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to cause an impact ionization phenomenon in the semiconductor base with a current flowing between the first impurity layer and the second impurity layer, an operation in which, out of a group of electrons or holes that are generated, the group of electrons is removed from the first impurity layer or the second impurity layer, and an operation in which part or all of the group of holes is left in the semiconductor base, and
the semiconductor memory device performs a memory erase operation in which the voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to discharge a left group of holes of the group of holes from one or both of the first impurity layer and the second impurity layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/981,634Filed 7 Nov 2022
Priority: JP PCT/JP2021/0410859 Nov 2021
Published: 11 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
H10B 12/20
Dynamic random access memory [DRAM] devices: dRAM devices comprising floating-body transistors, e.g. floating-body cells
H10B 12/33
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the capacitor extending under the transistor