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AssigneeKioxia Corporation
InventorsSuguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
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According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
A method of controlling a memory device, the memory device including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation and including a plurality of word lines each connecting a plurality of memory cells, each of the plurality of memory cells configured to store data therein in accordance with a threshold voltage thereof, the plurality of blocks including at least a first block, the first block including at least a first word line connecting at least a first memory cell, said method comprising:
Dependencies are inferred from the claim text.