Nonvolatile memory device having multi-stack memory block and method of operating the same

A method of operating a nonvolatile memory device, the method comprising:

• dividing, into a plurality of memory stacks, a memory cell array comprising a plurality of cell strings in which a plurality of memory cells are disposed in a vertical direction, respectively, wherein inter-stack portions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks;
• determining, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks;
• and
• performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup time points for applying a pass voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines,
• wherein the pass voltage is set to a voltage by which the plurality of memory cells are turned on.

A method of operating a nonvolatile memory device, the method comprising:

• dividing, into a plurality of memory stacks, a memory cell array comprising a plurality of cell strings in which a plurality of memory cells are disposed in a vertical direction, respectively, wherein inter-stack portions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks;
• determining, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks;
• and
• performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling recovery time points for applying a recovery voltage to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.