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US 2023/0145418 A1Published application
Interference Reducing Passive Transmission Line Receiver
AssigneeSynopsys, Inc.
InventorStephen Whiteley
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Abstract
The present disclosure relates to improved electronic structures for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflecting signals that otherwise result in distortions in the signals being transmitted between the gates. Other improved electronic structures comprise passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuity minimizes generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.
Claims14
A three-junction interferometer, including:
- an input port;
- a reference potential terminal;
- a first Josephson junction having a first and second terminal, the first terminal coupled to the input port;
- a second Josephson junction having a first and second terminal, the first terminal of the second Josephson junction being coupled to the second terminal of the first Josephson junction and the second terminal of the second Josephson junction being coupled to the reference potential terminal;
- a first inductance having a first and second terminal, the first terminal of the first inductance being coupled to the second terminal of the first Josephson junction;
- and
- a third Josephson junction having a first and second terminal, the first terminal of the third Josephson junction being coupled to the second terminal of the first inductance and the second terminal of the third Josephson junction being coupled to the reference potential terminal.
4 more elements
A three-junction interferometer, including:
- (a) an input port;
- (b) a reference potential terminal;
- (c) a first Josephson junction having a first and second terminal, the first terminal coupled to the input port;
- (d) a second Josephson junction having a first and second terminal, the first terminal coupled to the second terminal of the first Josephson junction and the second terminal coupled to the reference potential terminal;
- (e) a first inductance having a first and second terminal, the first terminal coupled to the second terminal of the first Josephson junction;
- (f) a first current source having a current in port and a current out port, the current in port coupled to the second terminal of the second inductance;
- (g) a second inductance having a first and second terminal, the first terminal of the second inductance coupled to the first terminal of the current out port of the first current source;
- (h) a third Josephson junction having a first and second terminal, the first terminal coupled to the second terminal of the second inductance and the second terminal coupled to the reference potential terminal.
5 more elements
A digital logic circuit comprising:
- (a) a driver circuit configured to receive a single flux quantum (SFQ) input signal and convert the SFQ input signal into a non-SFQ voltage, the driver circuit comprising:
- (1) a first inductance having a first and second terminal;
- (2) a second inductance having a first and second terminal, the first terminal of the second inductance coupled to the second terminal of the first inductance;
- (3) a drive resistance having a first and second terminal, the first terminal of the drive resistance coupled to the second terminal of the second inductance;
- (4) a first Josephson junction having a first and second terminal, the first terminal of the first Josephson junction coupled to the second terminal of the first inductance, the second terminal of the first Josephson junction coupled to a reference potential;
- and
- (5) a second Josephson junction having a first and second terminal, the first terminal of the second Josephson junction coupled to the second terminal of the second inductance, the second terminal of the second Josephson junction coupled to a reference potential;
- (b) a passive transmission line (PTL) having a driver end and a receiver end, the receiver end coupled to the second terminal of the drive resistance and having an impedance that is matched to the impedance of the drive resistance;
- and
- (c) a receiver comprising:
- (1) a third Josephson junction having a first and second terminal, the first terminal of the third Josephson junction coupled to the receiver end of the PTL and the second terminal of the third Josephson junction coupled to the reference potential.
8 more elements
Dependencies are inferred from the claim text.