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US 2023/0145327 A1Published application
Semiconductor device and fabrication method thereof
AssigneeUnited Semiconductor (Xiamen) Co., Ltd.
InventorsWei-Chun Chang, You-Di Jhang, Chin-Chun Huang, WEN YI TAN
Life of this patent
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Abstract
A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.
Claims17
A semiconductor device, comprising:
- a substrate having a transistor forming region and a resistor forming region thereon;
- a transistor disposed on the substrate within the transistor forming region;
- a first inter-layer dielectric (ILD) layer covering the transistor forming region and the resistor forming region and around the transistor;
- a first etch stop layer disposed on the first ILD layer;
- a second inter-layer dielectric (ILD) layer disposed on the first etch stop layer;
- a contact plug in the second ILD layer, the first etch stop layer, and the first ILD layer to electrically connect with a terminal of the transistor;
- a third inter-layer dielectric (ILD) layer disposed on the second ILD layer;
- a first metal interconnect layer disposed in the third ILD layer and being electrically connected to the contact plug;
- a second etch stop layer disposed on the third ILD layer;
- a resistor disposed on the second etch stop layer within the resistor forming region;
- a fourth inter-layer dielectric (ILD) layer covering the resistor and the second etch stop layer;
- and
- a first via disposed in the fourth ILD layer and being electrically connect with a terminal of the resistor.
10 more elements
A semiconductor device, comprising:
- a substrate having a transistor forming region and a resistor forming region thereon;
- a transistor disposed on the substrate within the transistor forming region;
- a plurality of interlayer dielectric layers covering the transistor forming region and the resistor forming region;
- a contact plug disposed in at least one of the plurality of interlayer dielectric layers and electrically connected to a terminal of the transistor;
- a resistor disposed on at least one of the plurality of interlayer dielectric layers within the resistor forming region thereon;
- and
- a via disposed in at least one of the plurality of interlayer dielectric layers and electrically connected to a terminal of the resistor, wherein the contact plug and the via are disposed in different layers.
4 more elements
Dependencies are inferred from the claim text.