Memory cell array including partitioned dual line structure and design method thereof

An integrated circuit comprising:

• a first sub-array comprising a first structure that comprises a static random access memory (SRAM) cell and a second structure;
• a second sub-array neighboring the first sub-array in a second direction;
• a multiplexer portion configured to transmit signals to the first sub-array and the second sub-array according to a column address and a sub-array address;
• a plurality of first metal wirings spaced apart from each other along a first direction, and extending through the first structure and the second structure in a second direction perpendicular to the first direction, each of the plurality of first metal wirings comprising a first portion and a second portion that is separated from the first portion by a first cutting portion;
• a third metal wiring formed above the plurality of first metal wirings and extending in the second direction through the first structure and the second structure, and at least partially overlapping the plurality of first metal wirings along a third direction perpendicular to the first direction and the second direction;
• and
• a first bridge formed in the second structure between the plurality of first metal wirings and the third metal wiring, and electrically connecting the plurality of first metal wirings to the third metal wiring.

An integrated circuit comprising:

• a first metal wiring of a word line extending in a first direction through a first segment and a second segment of the integrated circuit, the first metal wiring comprising a first portion and a second portion that is separated from the first portion by a first cutting portion;
• a second metal wiring of the word line extending in the first direction, and at least partially overlapping the first metal wiring along a second direction perpendicular to the first direction;
• and
• two bridges formed in a stack structure between the first metal wiring and the second metal wiring, and electrically connecting the first metal wiring to the second metal wiring at both ends of the second segment.