Semiconductor device

A semiconductor device comprising:

• a memory cell array in which a plurality of memory cells is arranged in a matrix, wherein
• each memory cell of the plurality of memory cells includes
• a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other,
• two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar,
• two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other,
• two second transfer field effect transistors each having a gate electrode connected to the word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and
• two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar.

A semiconductor device comprising:

• a memory cell array in which a plurality of memory cells is arranged in a matrix, wherein
• each memory cell of the plurality of memory cells includes
• a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other,
• a first transfer field effect transistor having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode region being connected to the output portion of the other inverter circuit of the two inverter circuits, and the second main electrode region being connected to a bit line bar,
• two second drive field effect transistors each having a gate electrode and a pair of first and second main electrode regions, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the first main electrode regions being connected to each other,
• two second transfer field effect transistors each having a gate electrode connected to an axon line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the second main electrode regions of the two second drive field effect transistors, and
• two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two second transfer field effect transistors and other end sides are respectively connected to a dendrite line and a dendrite line bar.

A semiconductor device comprising:

• a memory cell array in which a plurality of memory cells is arranged in a matrix, wherein
• each memory cell of the plurality of memory cells includes
• a flip-flop circuit including two inverter circuits in which a load field effect transistor and a first drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other,
• two first transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and the second main electrode regions being respectively connected to a bit line and a bit line bar,
• two second drive tunnel field effect transistors each having a gate electrode and a pair of n-type first main electrode region and p-type second main electrode region, the gate electrodes being respectively connected to the input portions of the two inverter circuits, and the n-type first main electrode region being connected to an axon line, and
• two second transfer tunnel field effect transistors each having a gate electrode connected to the word line, and a pair of n-type first main electrode region and p-type second main electrode region, the p-type second main electrode regions being respectively connected to the p-type second main electrode regions of the two second drive tunnel field effect transistors, and the n-type first main electrode regions being respectively connected to a dendrite line and a dendrite line bar.