Memory device, a controller for controlling the same, a memory system including the same, and an operating method of the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYesin RYU, Sunggi AHN, Jaeyoun YOUN
Life of this patent
Estimating the term…
Abstract
A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.
Claims13
A memory device, comprising:
- a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines;
- an error correction circuit configured to read data from the memory cell array and to correct an error in the read data;
- and
- an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array,
- wherein the ECS circuit comprises:
- a first register configured to store an error address;
- and
- an ECS logic configured to perform the scrubbing operation while operating an ECS address counter from the error address in a first direction or a second direction.
An operating method of a memory device, the operating method comprising:
- receiving error check and scrub (ECS) mode information from a controller;
- receiving a page offline address from the controller;
- performing a scrubbing operation in response to the ECS mode information;
- and
- reporting an error address detected in the scrubbing operation to the controller.
A memory system, comprising:
- a memory device;
- and
- a controller configured to control the memory device, to receive an error address from the memory device, and to transmit a mapped-out page offline address to the memory device,
- wherein the memory device includes a memory cell array, an error correction circuit configured to read data from the memory cell array and to correct an error in the read data, and an error check and scrub (ECS) circuit including a first register, configured to perform a scrubbing operation on the memory cell array and to store an error address detected in the scrubbing operation, and a second register configured to store the page offline address from the controller.
Dependencies are inferred from the claim text.