Electronic fuse structure embedded in top via
AssigneeInternational Business Machines Corporation
InventorsKoichi Motoyama, CHANRO PARK, Hsueh-Chung Chen, Chih-Chao Yang
Life of this patent
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Abstract
Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.
Claims20
A semiconductor device comprising:
- a plurality of bottom lines;
- one or more top vias arranged on top of the plurality of bottom lines;
- one or more electronic fuses (eFuses) arranged on top of the plurality of bottom lines, wherein each of the one or more eFuses is a via having a critical dimension smaller than the one or more top vias;
- and
- a plurality of top lines arranged on top of the one or more top vias and the one or more eFuses.
A method for fabricating an electronic fuse (eFuse), the method comprising:
- forming one or more dummy vias on top of one or more bottom lines on a substrate;
- selectively etching a first dummy via of the one or more dummy vias to reduce a size of the first dummy via;
- depositing a dielectric layer around the one or more dummy vias;
- removing the first dummy via to create a first eFuse vacancy;
- depositing a conductive material in the first eFuse vacancy to create an eFuse;
- and
- forming one or more top lines, wherein one top line of the one or more top lines is formed on top of the eFuse.
A method for fabricating an electronic fuse (eFuse), the method comprising:
- forming one or more dummy vias on top of one or more bottom lines on a substrate;
- encapsulating the one or more dummy vias in a dielectric material;
- performing a planarization process to remove a portion of the dielectric material and expose a top surface of the one or more dummy vias;
- removing a first dummy via to create a first eFuse vacancy;
- depositing a spacer material in the first eFuse vacancy, wherein the spacer material is deposited along sidewalls of the first eFuse vacancy but does not fill the first eFuse vacancy;
- depositing a conductive material in the first eFuse vacancy to create an eFuse;
- and
- forming one or more top lines, wherein one top line of the one or more top lines is formed on top of the eFuse.
Dependencies are inferred from the claim text.