Software-directed register file sharing
AssigneeNVIDIA Corporation
InventorsSana Damani, Sean Treichler, Mark Stephenson
Life of this patent
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Abstract
A computing system including one or more processor and one or more memory that stores application code that configures the processor to execute an application. The system includes logic to identify high and low register utilization regions of the application code and insert register acquire instructions and register release instructions in the application code by the compiler, such that when executed by the processor, the application code borrows and returns registers to an inter-block register pool when execution enters a high and low register utilization region, respectively.
Claims20
A system comprising:
- a processor;
- a memory comprising application code that configures the processor to execute an application;
- and
- logic to generate register acquire instructions and register release instructions in the application code, such that when executed by the processor, the application code borrows and returns registers to an inter-block register pool when execution enters a particular section of the application code.
A system comprising:
- a processor;
- a memory comprising application code that configures the processor to execute an application;
- logic to insert register acquire instructions into the application code;
- and
- logic to generate in the application code a slow execution path that employs register spill and refill instructions and is only executed on condition that the register acquire instructions fail.
A method comprising:
- inserting register acquire instructions and register release instructions for an inter-block register pool into a first section of application code;
- and
- launching execution of the application code with a register allocation based on register utilization of a second section of the application code that employs register spill and refill instructions.
Dependencies are inferred from the claim text.