Volatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJAE PIL LEE, HI JUNG KIM, KWANG SOOK NOH
Life of this patent
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Abstract
A volatile memory device may include; a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier in a first direction, a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, a third sense amplifier spaced apart from the second sense amplifier in a second direction, a fourth sense amplifier spaced apart from the third sense amplifier in the first direction, and a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.
Claims20
A volatile memory device comprising:
- a first sense amplifier;
- a second sense amplifier spaced apart from the first sense amplifier in a first direction;
- a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier;
- a third sense amplifier spaced apart from the second sense amplifier in a second direction;
- a fourth sense amplifier spaced apart from the third sense amplifier in the first direction;
- and
- a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.
A volatile memory device comprising:
- a row decoder extending in a first direction;
- a column decoder extending in a second direction;
- and
- a memory cell array between the row decoder and the column decoder,
- wherein the memory cell includes:
- a center region including a first sense amplifier, a first mat including a first bit line connected to the first sense amplifier, and a second mat including a first complementary bit line connected to the first sense amplifier;
- and
- a first edge region disposed in the first direction from the center region,
- wherein the first edge region includes a second sense amplifier and a third mat including a second bit line connected to the second sense amplifier and disposed in a third direction opposite to the first direction from the second sense amplifier, and
- the second sense amplifier is connected to the first complementary bit line of the center region.
A volatile memory device comprising:
- a first sense amplifier;
- a second sense amplifier spaced apart from the first sense amplifier in a first direction;
- a third sense amplifier spaced apart from the first sense amplifier in the first direction and spaced apart from the second sense amplifier in a second direction;
- a first mat formed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier;
- a second mat formed between the first sense amplifier and the third sense amplifier and including a first complementary bit line connected to the first sense amplifier and a third bit line connected to the third sense amplifier;
- a third mat spaced apart from the second sense amplifier in the first direction and including a second complementary bit line connected to the second sense amplifier;
- a fourth mat spaced apart from the third sense amplifier in the first direction and including a third complementary bit line connected to the third sense amplifier;
- a first word line connected to the first mat and the fourth mat;
- and
- a second word line connected to the second mat and the third mat.
Dependencies are inferred from the claim text.