Non-volatile memory device for detecting defects of bit lines and word lines

A non-volatile memory device comprising:

• a memory cell array provided in a first semiconductor layer and comprising a plurality of cell strings, each comprising a plurality of memory cells respectively connected to a plurality of word lines;
• a page buffer circuit provided in a second semiconductor layer and connected to each of a plurality of bit lines via through electrodes penetrating the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer is provided on the second semiconductor layer;
• a control logic circuit provided in the second semiconductor layer, and configured to control a pre-sensing operation to disconnect the plurality of bit lines and the plurality of cell strings from each other during a pre-sensing period for detecting a defect of at least one of the plurality of bit lines and control a post-sensing operation to connect the plurality of bit lines and the plurality of cell strings in a post-sensing period for detecting defects of at least one of the plurality of word lines and the plurality of bit lines;
• and
• a defect detection circuit provided in the second semiconductor layer and configured to detect defects of the plurality of word lines based on a result of the pre-sensing operation and a result of the post-sensing operation.

A non-volatile memory device comprising:

• a memory cell array comprising a first memory cell connected to a first word line and a second memory cell connected to a second word line;
• a page buffer circuit comprising a first page buffer connected to the first memory cell and a first cell string through a first bit line, and a second page buffer connected to the second memory cell and a second cell string through a second bit line;
• a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string in a post-sensing period for detecting defects of the first word line and the first bit line;
• and
• a defect detection circuit configured to detect defects of the first word line based on a result of the pre-sensing operation and a result of the post-sensing operation.