Logic circuit locking with self-destruct

Abstract

An approach for validating a logic key in an IC (integrated circuit) is disclosed. One approach includes an IC comprising of key input circuit couple to a fuse check circuit; charge pump circuit coupled to the fuse check circuit and a switch matrix; and one or more antifuse circuit connected to the switch matrix. Another approach comprises of a method including, inputting a secret key by a user; determining status of one or more antifuse circuit; validating the secret key; in responsive to the secret key not matching an original secret key, determining whether antifuse threshold has been reached; in responsive to determining that the antifuse threshold has been reached, disabling the IC; in responsive to the secret key matching the original secret key, enabling the IC; and in responsive to determining that the antifuse threshold has not been reached, activating the antifuse circuit.

Dependencies are inferred from the claim text.