Memory controller and memory system including the same

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cell rows, each including a plurality of volatile memory cells;
• a row hammer management engine configured to:
• predict a first probability of occurrence of a row hammer in which at least one of the plurality of memory cell rows is intensively accessed by a first row access pattern on at least a second portion on the plurality of memory cell rows during a first reference time interval posterior to a first refresh interval during which at least a first portion of the plurality of memory cell rows are refreshed, based on machine learning, and
• generate a hammer address associated with the row hammer, an outcast row list, and an alert signal indicating that the row hammer occurs, the outcast row list being associated with outcast memory cell rows from among the plurality of memory cell rows which are excluded from a hammer refresh operation for coping with the row hammer;
• and
• a refresh control circuit configured to receive the hammer address, the alert signal and the outcast row list, configured to perform the hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address, and configured to perform a target refresh operation on the outcast memory cell rows based on the outcast row list.

A memory system comprising:

• a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each including a plurality of volatile memory cells;
• and
• a memory controller configured to control the semiconductor memory device, wherein the memory controller includes:
• an access pattern profiler configured to generate a first access pattern profile based on a first row access pattern associated with a first access on at least a second portion of the plurality of memory cell rows during a first reference time interval posterior to a first refresh interval during which at least a first portion of the plurality of memory cell rows are refreshed,
• a row hammer prediction neural network configured to:
• perform machine learning based on learning data;
• predict a first probability of occurrence of a row hammer in which at least one of the plurality of memory cell rows is intensively accessed by the first row access pattern, based on the first access pattern profile;
• and
• in response to the first probability being equal to or greater than a reference value, generate a hammer address associated with the row hammer, an outcast row list, and an alert signal indicating that the row hammer occurs, the outcast row list being associated with outcast memory cell rows from among the plurality of memory cell rows, which are excluded from a hammer refresh operation that is performed in the semiconductor memory device in response to the first row access pattern, and
• a memory interface configured to transmit the hammer address, the outcast row list, and the alert signal to the semiconductor memory device, wherein:
• the semiconductor memory device is configured to, in response to the alert signal:
• perform the hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address;
• and
• perform a target refresh operation on the outcast memory cell rows based on the outcast row list.