Computer processing devices with dynamic shared cache line copy retention policy selection
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn Kelley, Paul Moyer
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Abstract
Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.
Claims20
A method comprising:
- determining a cache line sharing parameter indicative of a quantity of shared cache lines in a plurality of caches of a computer processing device;
- and
- setting a shared cache line copy retention policy for a cache that is coupled to the plurality of caches based on the cache line sharing parameter.
A method comprising:
- implementing set dueling in a core complex of a computer processing device to select a shared cache line copy retention policy for a set of caches of a first level and a cache of a second level.
A computer processing device comprising:
- a set of caches of a first level;
- and
- a cache of a second level coupled to the set of caches of the first level, the computer processing device being configured to dynamically select a shared cache line copy retention policy that determines whether shared cache lines of at least one cache of the set of caches of the first level are retained in the cache of the second level.
Dependencies are inferred from the claim text.