Methods for programming a memory device, memory devices, and memory systems
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsKe Jiang, Xiaodong Mei, Xiaojiang Guo
Life of this patent
Estimating the term…
Abstract
A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.
Claims20
A method for programming a memory device comprising planes, the method comprising:
- programming the planes by using a programming voltage incremented with a first step size;
- verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception;
- and
- in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size;
- wherein the second step size is less than the first step size.
A memory device, comprising:
- a memory array comprising planes;
- a row driver configured to apply voltages to the planes;
- and
- a control logic circuit configured to:
- control the row driver to apply a programming voltage incremented with a first step size to program the planes,
- verify the planes, and in response to determining that the one or more planes are with a verification exception, disable the one or more planes with the verification exception, and
- in response to the one or more planes being disabled, control the row driver to apply an other programming voltage incremented with a second step size to further program remaining one or more planes that are not disabled,
- wherein the second step size is less than the first step size.
A memory system, comprising:
- one or more memory devices;
- and
- a memory controller coupled to the memory devices;
- wherein each of the memory devices comprises:
- a memory array comprising planes;
- a row driver configured to apply voltages to the planes;
- and
- a control logic circuit configured to:
- control the row driver to apply a programming voltage incremented with a first step size to program the planes,
- verify the planes, and in response to determining that the one or more planes are with a verification exception, disable the one or more planes with the verification exception, and
- in response to the one or more planes being disabled, control the row driver to apply an other programming voltage incremented with a second step size to further program remaining one or more planes that are not disabled,
- wherein the second step size is less than the first step size.
Dependencies are inferred from the claim text.