Method for improving bridging between source/drain epitaxial layer and gate

A method for improving bridging defects between a source/drain epitaxial layer and a gate of fin field effect transistors, wherein the fin field effect transistors comprise a N-type fin field effect transistor and a P-type fin field effect transistor, wherein the method comprises:

• S1:
• providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, and forming an insulating layer between lower portions of adjacent two of the plurality of fins to isolate each fin, wherein the plurality of fins is arranged in parallel to each other;
• S2:
• forming a polysilicon gate layer, forming a plurality of polysilicon gate rows by an etching process, wherein the plurality of polysilicon gate rows is arranged in parallel, wherein a length direction of the plurality of polysilicon gate rows is perpendicular to a length direction of the plurality of fins, wherein dummy gate structures are respectively formed in intersection areas of the plurality of polysilicon gate rows and the plurality of fins;
• S3:
• performing an etching process to the insulating layer between the lower portions of the adjacent two of the plurality of fins to remove a part of the insulating layer of a first thickness and to retain another part of the insulating layer;
• S4:
• forming sidewalls, wherein the sidewalls are disposed on exposed surfaces of the plurality of fins, a surface of the insulating layer between adjacent two of the plurality of fins, and surfaces of the plurality of polysilicon gate rows;
• S5:
• forming a hard mask layer on the sidewalls;
• S6:
• forming source regions or drain regions on two sides of each of the dummy gate structures on the plurality of fins, wherein an embedded trench is formed in the source regions or in the drain regions;
• and
• S7:
• forming an embedded epitaxial layer in the embedded trench of the source regions or the drain regions.