Integrated circuit
AssigneeFuji Electric Co., Ltd.
InventorHiroyuki NAKAJIMA
Life of this patent
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Abstract
An integrated circuit having: a signal output circuit configured to output a first digital signal of a first logic level or of a second logic level in response to an analog signal; a first buffer circuit configured to raise and lower a voltage at a terminal of the integrated circuit in response to the first digital signal of a first logic level and a second logic level, respectively; a first digital delay circuit configured to receive a clock signal, and to delay the first digital signal, to output a resultant signal as a first delay signal, based on the received clock signal; and a second buffer circuit configured to raise the voltage at the terminal in response to the first delay signal of the first logic level, and lower the voltage at the terminal in response to the first delay signal of the second logic level.
Claims8
An integrated circuit having a terminal, the integrated circuit comprising:
- a signal output circuit configured to output a first digital signal of a first logic level or a second logic level in response to an analog signal;
- a first buffer circuit configured to
- raise a voltage at the terminal in response to the first digital signal of the first logic level, and
- lower the voltage at the terminal in response to the first digital signal of the second logic level;
- a first digital delay circuit configured to receive a clock signal, and to delay the first digital signal, to thereby output a resultant signal as a first delay signal, based on the received clock signal;
- and
- a second buffer circuit configured to
- raise the voltage at the terminal in response to the first delay signal of the first logic level, and
- lower the voltage at the terminal in response to the first delay signal of the second logic level.
Dependencies are inferred from the claim text.