Memory device, a memory system having the same and an operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorSeungki HONG
Life of this patent
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Abstract
An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.
Claims20
An operating method of a memory device, the method comprising:
- receiving a row address;
- determining whether an operating mode is a byte mode;
- counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode;
- selecting a target row hammer address, among target row addresses, using access count values for the target row hammer address;
- calculating a victim row address corresponding to the target row hammer address;
- and
- performing a target refresh operation on the victim row address.
A memory device, comprising:
- a first row address control unit configured to receive a row address and to output a signal indicating a first count-up scheme;
- a second row address control unit configured to receive the row address and to output a signal indicating a second count-up scheme while ignoring a page separation bit of the row address;
- counter control units configured to control a count-up operation for respective target row addresses by one of the first and second count-up schemes;
- counter and registers configured to increase an access count value according to control of each of the counter control units and to store the target row addresses and corresponding counted-up access count values;
- and
- a selector configured to select a target row address, corresponding to one access count value among access count values respectively stored in the counter and registers, as a row hammer address.
A memory system, comprising:
- at least one memory device;
- and
- a memory controller configured to control the at least one memory device, wherein:
- the at least one memory device detects a row hammer address while not considering a page separation bit of a row address in a byte mode operation, generates a victim address corresponding to the detected row hammer address, and performs a target refresh operation on the victim address.
Dependencies are inferred from the claim text.