Semiconductor memory device and memory system having the same

A memory device comprising:

• a plurality of memory blocks, each of the plurality of memory blocks having memory cells connected a plurality of wordlines and a plurality of bitlines;
• a row decoder configured to select one wordline among the plurality of wordlines according to a row address;
• a plurality of sense amplification circuits configured to select at least one of the plurality of bitlines according to a column address;
• a command and address generator configured to receive a command and address from a memory controller, to decode the command and address to generate the row address with an active command, and to generate the column address with a read command or a write command;
• and
• a refresh controller configured to perform a first refresh operation on the plurality of memory blocks in response to a refresh command and to perform a second refresh operation on at least one of the plurality of memory blocks in response to the refresh command.

A memory system comprising:

• at least one memory device;
• and
• a memory controller configured to control the at least one memory device,
• wherein the at least one memory device is configured to receive a refresh command from the memory controller, to perform a first refresh operation on a plurality of memory blocks in response to the refresh command, and to perform a second refresh operation on at least one of the plurality of memory blocks in response to the refresh command, and
• wherein the first refresh operation and the second refresh operation are sequentially performed by time-division.