Nonvolatile memory device and method of operating nonvolatile memory device

A nonvolatile memory device comprising:

• a memory cell array that includes at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line;
• and
• a control circuit configured to:
• during a word-line set-up period, set up each of a plurality of word-lines coupled to the plurality of memory cells to a respective target level;
• during a sensing period, perform a sensing operation on target memory cells of the plurality of memory cells by applying a read voltage to a selected word-line coupled to the target memory cells, among the plurality of word-lines while applying a read pass voltage to unselected word-lines among the plurality of word-lines;
• during a word-line recovery period, perform a word-line recovery operation by recovering a voltage level of the unselected word-lines to a level of an internal voltage;
• and
• during a discharge period within the word-line recovery period, consume the internal voltage connected to the unselected word-lines to which the read pass voltage is applied, in a particular circuit of the nonvolatile memory device,
• wherein the particular circuit connected to the internal voltage is configured to be activated during the discharge period, and the particular circuit is not associated with the word-line recovery operation.

A nonvolatile memory device comprising:

• a memory cell array that includes at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line;
• and
• a control circuit configured to:
• during a word-line set-up period, set up each of a plurality of word-lines coupled to the plurality of memory cells to a respective target level;
• during a sensing period, perform a sensing operation on target memory cells of the plurality of memory cells by applying a read voltage to a selected word-line coupled to the target memory cells, among the plurality of word-lines while applying a read pass voltage to unselected word-lines among the plurality of word-lines;
• and
• during a word-line recovery period, perform a word-line recovery operation by recovering a voltage level of the unselected word-lines to a level of an external voltage applied from an external device and to a level of an internal voltage smaller than the level of the external voltage, sequentially.