US 2023/0143181 A1 · WRITE BUFFER CONTROL IN MANAGED MEMORY SYSTEM

Abstract

Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.

Claims20

Dependent claims

A memory device comprising:

a memory array comprising at least single-level cell (SLC) data blocks and multiple level cell (MLC) data blocks;
a write buffer;
and
a memory controller configured to receive commands from a host device and to execute instructions retained within the memory device that, when executed, implement operations including:
enabling the write buffer to receive host data from the host device;
upon receipt of a command to synchronize a cache, determining whether the write buffer is full of host data above a predetermined threshold;
when the write buffer is full of host data above the predetermined threshold, flushing host data in the write buffer to an open MLC data block;
and
when the write buffer is not full of host data above the predetermined threshold, flushing host data in the write buffer to a temporary storage location.

6 more elements

At least one non-transitory device-readable storage medium comprising instructions that, when executed by a memory controller of a storage system comprising at least single-level cell (SLC) data blocks, multiple-level cell C) data blocks, and a write buffer,

cause the memory controller to perform operations comprising:
upon receipt of a command from a host device to synchronize a cache, determining whether the write buffer is full of host data above a predetermined threshold;
when the write buffer is full of host data above the predetermined threshold, flushing host data in the write buffer to an open MLC data block;
and
when the write buffer is not full of host data above the predetermined threshold, flushing host data in the write buffer to a temporary storage location.

2 more elements

Dependencies are inferred from the claim text.

Write buffer control in managed memory system

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Write buffer control in managed memory system

Life of this patent

Abstract

Claims20