Devices with track-based fill (tbf) metal patterning
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Yi HU, Chih-Ming CHAO, Jung-Chou TSAI
Life of this patent
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Abstract
Disclosed are semiconductor devices having an interconnection pattern that includes a plurality of parallel conductors including a first conductor aligned with a first axis and a first dummy pattern aligned with a second axis on a first side of the first axis and offset from the first axis by an axis offset distance LAO in which the first dummy pattern includes N dummy conductors having a first dummy conductor length LDC with the dummy conductors being separated by a dummy conductor-to-dummy conductor spacing EED.
Claims20
A semiconductor device comprising:
- an interconnection pattern, comprising a plurality of parallel conductors;
- a first conductor aligned with a first axis;
- and
- a first dummy pattern aligned with a second axis and offset from a first side of the first axis by an axis offset distance LAO;
- wherein the first dummy pattern comprises N dummy conductors having a first dummy conductor length LDC and separated by a dummy conductor-to-dummy conductor spacing EED.
A semiconductor device comprising:
- an interconnection pattern comprising a plurality of parallel conductors;
- a first conductor aligned with a first axis;
- a first dummy pattern aligned with a second axis and offset from a first side of the first axis by a first integer multiple of an axis offset distance LAO;
- wherein the first dummy pattern comprises N dummy conductors having a first dummy conductor length LDC1 and separated by a first dummy conductor-to-dummy conductor spacing EED1;
- and
- a second dummy pattern aligned with a third axis and offset from a second side of the first axis by a second integer multiple of the axis offset distance LTO;
- wherein the second dummy pattern comprises M dummy conductors having a second dummy conductor length LDC2 and separated by a second dummy conductor-to-dummy conductor spacing EED2.
A semiconductor device comprising:
- an interconnection pattern comprising
- a plurality of parallel conductors;
- a first conductor and a second conductor aligned with a first axis;
- a first dummy pattern aligned with the first axis and arranged between the first conductor and second conductor,
- wherein the first dummy pattern comprises N dummy conductors having a first dummy conductor length LDC1 and separated by a first dummy conductor-to-dummy conductor spacing EED1, and wherein a first dummy conductor is separated from the first conductor by a first end-to-end spacing EE1 and a last dummy conductor is separated from the second conductor by the first end-to-end spacing EE1;
- and
- a second dummy pattern aligned with a second axis and offset from a first side of the first axis by a first integer multiple of an axis offset distance LAO;
- wherein the second dummy pattern comprises M dummy conductors having a second dummy conductor length LDC2 and being separated by a second dummy conductor-to-dummy conductor spacing EED2.
Dependencies are inferred from the claim text.