Circuits and methods for multiplying large integers over a finite field
AssigneeXilinx, Inc.
InventorMing Ruan
Life of this patent
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AssigneeXilinx, Inc.
InventorMing Ruan
Estimating the term…
Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through Kby determining respective sets of intermediate z-limbs 0 through K- 1 for r-limbs i for i = 0 to K - 1, and summing corresponding ones of the intermediate z-limbs of sets i through K - 1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K - 1 of set 0 as products of r-limb 0 and a-limbs 0 through K - 1, and for the remaining r-limbs determines intermediate z-limbs using different combinations of a-limbs, r-limbs, modulus, and d-limbs. A modulo circuit computes G as (most significant M bits of Z* m) + (least significant Q bits of Z, wherein M is a number of bits by which a number of bits of Z exceeds N, and Q is equal to M + ceil (log2 m), and increases G by m if bits Q through N - 1 of Z all having bit value one, and G ≥ 2Q - m. Circuitry assigns bits G bits 0 through Q-1 to Y bits 0 through Q- 1, and G bit Q to Y bit Q.
A circuit arrangement comprising:
A method comprising:
Dependencies are inferred from the claim text.