Vertical transistors having improved control of parasitic capacitance and gate-to-contact short circuits
AssigneeInternational Business Machines Corporation
InventorsChoongHyun Lee, Ardasheir Rahman, Xin Miao, Brent A. Anderson, Alexander Reznicek
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.
Claims20
A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise:
- forming a channel fin;
- forming a gate structure along a sidewall surface of the channel fin;
- wherein the gate structure comprises a conductive gate having an L-shape profile;
- wherein the L-shape profile comprises a conductive gate foot region;
- and
- replacing the conductive gate foot region with a dielectric foot region.
A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise:
- forming a first channel fin;
- forming a second channel fin;
- forming a first gate structure along a sidewall surface of the first channel fin;
- wherein the first gate structure comprises a first conductive gate having a first L-shape profile;
- wherein the first L-shape profile comprises a first conductive gate foot region;
- forming a second gate structure along a sidewall surface of the second channel fin;
- wherein the second gate structure comprises a second conductive gate having a second L-shape profile;
- wherein the second L-shape profile comprises a second conductive gate foot region;
- replacing the first conductive gate foot region with a first dielectric foot region;
- and
- replacing the second conductive gate foot region with a second dielectric foot region.
An integrated circuit (IC) comprising:
- a first channel fin;
- and
- a first gate structure along a sidewall surface of the first channel fin;
- wherein the first gate structure comprises a first conductive gate having a first L-shape profile;
- and
- wherein the first L-shape profile comprises a first conductive gate leg region and a first dielectric foot region.
Dependencies are inferred from the claim text.