Centrally logging and aggregating miscompares on chip during memory test

A memory device, comprising:

• one or more memory banks;
• and
• a built-in self-test (BIST) unit configured to:
• perform a memory test on the one or more memory banks of the memory device using a first algorithm;
• generate miscompare results responsive to performing the memory test on the one or more memory banks of the memory device;
• determine failure diagnostic information based on the miscompare results;
• generate an error packet comprising the failure diagnostic information and the miscompare results;
• and
• place the error packet in a queue of a plurality of error packets to generate a queued error packet.

A memory device, comprising:

• a plurality of memory banks;
• a plurality of comparators, each coupled to a respective memory bank of the plurality of memory banks;
• a plurality of error capture units, each coupled to a respective comparator of the plurality of comparators;
• and
• a queue coupled to the plurality of error capture units, wherein the queue configured to store one or more error packets associated with the plurality of memory banks;
• wherein each comparator configured to:
• perform a memory test on the respective memory bank to generate a respective set of comparison results;
• and
• send the respective set of comparison results to the respective error capture unit;
• wherein each error capture unit configured to:
• determine a respective set of failure diagnostic information based on the respective set of comparison results;
• generate a respective error packet comprising the respective set of failure diagnostic information and the respective set of comparison results;
• and
• place the respective error packet in the queue.