Gate-all-around nanosheet-fet with variable channel geometries for performance optimization

A semiconductor device comprising:

• a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1;
• and
• a second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2;
• wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other;
• and
• wherein the substrate includes a tapered surface in the Y-direction.

A method comprising:

• forming a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1;
• and
• forming a second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2;
• wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other;
• and
• wherein the substrate includes a tapered surface in the Y-direction.