Method of fabricating gates

A method of fabricating a device comprising a plurality of semiconductor-superconductor nanowires, each comprising a respective semiconductor core and a coating of superconductor material over the respective core;

• the method comprising:
• forming a first mask over a substrate, the substrate defining a plane, wherein the first mask is formed from an amorphous material and has a pattern of first openings formed over trenches in the substrate, and the substrate comprises a crystalline material at least at a surface of the trenches;
• forming a monocrystalline conducting material in the first openings by selective area growth, in order to thereby form gates for the nanowires in the trenches of the substrate;
• forming a second mask over the substrate and gates, the second mask also being amorphous and having a pattern of second openings;
• forming an insulating crystalline buffer in the second openings;
• forming a crystalline semiconductor material on the buffer in the second openings by selective area growth in order to form the cores of the nanowires, wherein the gates intersect with the cores in the plane of the substrate;
• and
• forming the coating of superconductor material over at least part of each of the cores.