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AssigneeYangtze Memory Technologies Co., Ltd.
InventorsDongXue ZHAO, Tao Yang, Yuancheng Yang, Lei Liu, Di Wang, Kun Zhang, Wenxi Zhou, Zhiliang Xia, ZongLiang Huo
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This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.
A method for performing a programming operation on a memory device, wherein the memory device comprises a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, and a bit line formed above the pillar, the method comprising:
A method for performing an erasing operation on a memory device, wherein the memory device comprises a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap, the method comprising:
A method for performing a programming operation on a memory device, wherein the memory device comprises a plate line, a bias gate above the plate line, a word line above the plate line, a pillar extending through the plate line, the bias gate, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap, the method comprising:
A method for performing an erasing operation on a memory device, wherein the memory device comprises a plate line, a bias gate above the plate line, a word line above the plate line, a pillar extending through the plate line, the bias gate, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap, the method comprising:
Dependencies are inferred from the claim text.