Semiconductor packages having upper conductive patterns

A semiconductor package comprising:

• a lower package;
• and
• an upper package on the lower package,
• wherein the lower package includes
• a lower redistribution structure including a wiring layer, and a via connected to the wiring layer,
• a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, first upper conductive patterns disposed on the base layer, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad,
• a first semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate,
• an encapsulant covering the lower redistribution structure, the connection substrate and the first semiconductor chip, and
• an upper redistribution structure on the encapsulant,
• wherein the upper redistribution structure includes a redistribution via connected to the second upper conductive pattern.

A semiconductor package comprising:

• a lower redistribution structure including a wiring layer, and a via connected to the wiring layer;
• an outer connection terminal below the lower redistribution structure;
• a connection substrate on the lower redistribution structure, the connection substrate including base layers, lower conductive patterns in the base layers, first upper conductive patterns disposed on an uppermost one of the base layers, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad;
• a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate;
• an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip;
• and
• an upper redistribution structure on the encapsulant,
• wherein the upper redistribution structure includes an insulating layer covering an upper surface of the encapsulant, a wiring layer on the insulating layer, and a redistribution via interconnecting the wiring layer and the second upper conductive pattern.