Gate-cut and separation techniques for enabling independent gate control of stacked transistors

A device comprising:

• an independent gate device comprising first vertically stacked transistors and a first center dielectric layer connecting one first vertical layer to another first vertical layer, the first center dielectric layer separating first transistors in the first vertically stacked transistors;
• and
• a shared gate device comprising second vertically stacked transistors and a second center dielectric layer separating second transistors of the second vertically stacked transistors.

A device comprising:

• an independent gate device comprising first vertically stacked transistors and a first center dielectric layer connected to a first vertical layer;
• and
• a shared gate device comprising second vertically stacked transistors and a second center dielectric layer, shared gate material being present at a space between the second center dielectric layer and a second vertical layer.