US 2023/0141852 A1 · MULTI-CHANNEL FIELD EFFECT TRANSISTORS WITH ENHANCED MULTI-LAYERED SOURCE/DRAIN REGIONS

Abstract

A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

Claims20

Dependent claims

A semiconductor device, comprising:

an active region extending in a first direction on a substrate;
a plurality of channel layers spaced apart from each other in a vertical direction orthogonal to an upper surface of the substrate, on the active region;
a gate structure intersecting the active region and the plurality of channel layers, surrounding the plurality of channel layers, and extending in a second direction, on the substrate;
and
a source/drain region extending on the active region and on at least one side of the gate structure, and contacting the plurality of channel layers, said source/drain region including:
a first epitaxial layer extending on the active region and in contact with the plurality of channel layers, and having a first upper surface configured to be recessed;
a second epitaxial layer in contact with a first portion of the first upper surface of the first epitaxial layer and having a second upper surface configured to be recessed;
and
a third epitaxial layer in contact with:
(i) a second portion of the first upper surface of the first epitaxial layer, and (ii) the second upper surface of the second epitaxial layer.

7 more elements

A semiconductor device, comprising:

an active region extending in a first direction on a substrate;
a stacked plurality of channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, on the active region;
a gate structure intersecting the active region and the plurality of channel layers, surrounding the plurality of channel layers, respectively, and extending in a second direction, on the substrate;
and
a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, said source/drain region comprising:
a first epitaxial layer disposed on the active region and extending to be in contact with the plurality of channel layers;
a second epitaxial layer disposed on the first epitaxial layer;
a third epitaxial layer disposed on the second epitaxial layer;
and
a fourth epitaxial layer disposed on the third epitaxial layer;
and
wherein the third epitaxial layer includes:
(i) a first surface in contact with the fourth epitaxial layer, (ii) a second surface in contact with the first epitaxial layer, and (iii) a third surface in contact with the second epitaxial layer.

10 more elements

Dependencies are inferred from the claim text.

Multi-channel field effect transistors with enhanced multi-layered source/drain regions

Life of this patent

Multi-channel field effect transistors with enhanced multi-layered source/drain regions

Life of this patent

Abstract

Claims20