Semiconductor memory device and method of operating the same

A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each including a plurality of volatile memory cells, the method comprising:

• capturing row addresses accompanied by first active commands randomly selected from active commands, each having a first selection probability that is uniform, from an external memory controller during a reference time interval;
• selecting at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval;
• and
• performing a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cell rows, each including a plurality of volatile memory cells;
• a row hammer management circuit configured to:
• capture row addresses accompanied by first active commands randomly selected from active commands, each having a first selection probability that is uniform, from an external memory controller during a reference time interval;
• select at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval;
• and
• determine a hammer address associated with least one of the plurality of memory cell rows, which is intensively accessed, based on counted values obtained by counting the active commands;
• and
• a refresh control circuit configured to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address, wherein:
• the first selection probability corresponds to a ratio of a number of the hammer refresh operation to be performed on the plurality of memory cell rows during a refresh period of the semiconductor memory device to an average access count of the plurality of memory cell rows during the reference time interval, and
• the row hammer management circuit is configured to select a portion of the row addresses accompanied by the first active commands, which are randomly selected based on a random binary code that varies randomly in response to the active commands, matching a reference binary code.