System on chip for performing scan test and method of designing the same

A system on chip, comprising:

• a first combinatorial logic;
• a second combinatorial logic;
• a third combinatorial logic;
• first scan flip-flops connected between the first combinational logic and the second combinational logic;
• second scan flip-flops connected between the second combinational logic and the third combinational logic;
• a scan control flip-flop configured to receive output data of the second combinational logic and to transfer the output data to the third combinational logic;
• a scan chain configured to receive scan data and including the first scan flip-flops and the second scan flip-flops;
• and
• a multiplexer configured to output one of an output signal of the scan chain and an output signal of the third combinational logic in response to a scan mode signal,
• wherein the scan control flip-flop is designed such that the output data does not affect a scan operation in a scan mode.

A method of designing a system on chip, the method comprising:

• defining one-time programmable (OTP) data in a specification;
• indicating whether the OTP data affects test or debugging access;
• and
• designing a shadow register using scan control flip-flops in storing the OTP data when the OTP data affects the test or debugging access,
• wherein each of the scan control flip-flops is designed such that output data does not affect the scan operation in the scan mode.