Compensation methods for voltage and temperature (vt) drift of memory interfaces

A data processor adapted to be coupled to a memory, comprising:

• a reference clock generation circuit for providing a reference clock signal;
• a first delay circuit for delaying said reference clock signal by a first amount to provide a command and address signal;
• a second delay circuit for delaying said reference clock signal by a second amount to provide a read data signal;
• a calibration circuit for determining current values of said first and second amounts;
• and
• a compensation circuit for calculating drifts in said first and second amounts based on a measured temperature change, at least one voltage sensitivity coefficient, and at least one temperature sensitivity coefficient, and for updating said first and second amounts according to said drifts.

A method for a data processor to update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation without performing link retraining, comprising:

• generating a reference clock signal;
• delaying said reference clock signal by a first amount using a first delay circuit to provide a command and address signal;
• delaying said reference clock signal by a second amount using a second delay circuit to provide a read data signal;
• determining current values of said first and second amounts using a calibration circuit;
• and
• calculating drifts in said first and second amounts based on a measured temperature change, at least one voltage sensitivity coefficient, and at least one temperature sensitivity coefficient using a compensation circuit.