Storage device and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorSoo-Young JI
Life of this patent
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Abstract
A storage device is provided. A storage device includes a non-volatile memory including a plurality of memory segments, and a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment, wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of the memory segments.
Claims20
A storage device comprising:
- a non-volatile memory including a plurality of memory segments;
- and
- a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment,
- wherein the storage controller is configured to generate parity according to speed information received from a host with respect to data to be written to the non-volatile memory and store the parity in at least one of plurality of memory segments via at least one of the plurality of channels.
A storage device comprising:
- a non-volatile memory including a plurality of memory segments;
- and
- a storage controller connected to the non-volatile memory through a plurality of channels, the storage controller being configured to acquire speed information and generate parity according to the speed information, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment,
- wherein the storage controller is further configured to generate erasure code data by performing erasure coding on original data and to generate the parity according to the speed information with respect to the erasure code data and store the parity in at least one of the memory segments.
A storage device comprising:
- a non-volatile memory including a plurality of memory segments;
- and
- a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment,
- wherein the storage controller configured to receive speed information from a host and generate parity according to the speed information;
- a host interface configured to receive first data to be written to the non-volatile memory from the host and transfer second data read from the non-volatile memory to the host;
- and
- a memory interface configured to transfer third data to be written to the non-volatile memory or receive fourth data read from the non-volatile memory, wherein
- the host interface and the memory interface are configured such that as a speed change included in the speed information increases, an amount of data transferred and received by the memory interface increases more than an amount of data transferred and received by the host interface.
Dependencies are inferred from the claim text.