Memory device, memory system, and method of operating the memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsEUN CHU OH, Junyeong Seok, Younggul Song, Byungchul Jang
Life of this patent
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Abstract
A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.
Claims20
A method of operating a memory system including a memory device and a memory controller, the method comprising:
- programming, by the memory device, K logical pages stored in a page buffer circuit into a memory cell array;
- reading, by the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses;
- transmitting, by the memory controller, N−K logical pages to the memory device;
- and
- programming, by the memory device, N logical pages into the memory cell array, based on the read K logical pages and the N−K logical pages,
- wherein K is a positive integer and N is a positive integer greater than K.
A memory system comprising:
- a memory device including a memory cell array, a page buffer circuit configured to store data to be stored in the memory cell array or data read from the memory cell array, and an error detector configured to detect an error with respect to the data of the page buffer circuit;
- and
- a memory controller configured to provide, to the memory device, a command instructing performance of a program operation on N bit data, K bit data, and N−K bit data,
- wherein the memory device is configured to perform a first program operation on the K bit data in response to the command, read the K bit data from the memory cell array into the page buffer circuit after a first delay time elapses, provide the read K bit data to the memory controller based on an error in the read K bit data, receive corrected K bit data from the memory controller and store the corrected K bit data in the page buffer circuit, and perform a second program operation on the N bit data, based on the K bit data stored in the page buffer circuit and the N−K bit data,
- wherein K is a positive integer and N is a positive integer greater than K.
A memory device comprising:
- a memory cell array including a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines;
- a page buffer circuit configured to temporarily store data to be stored in the memory cell array or data read from the memory cell array;
- an error detector configured to detect an error in data stored in the page buffer circuit;
- and
- a control logic circuit configured to, in response to a program command for N logical pages, perform a first program operation on the memory cell array based on K logical pages received from a memory controller and perform a second program operation on the memory cell array based on K logical pages, read from the memory cell array after a delay time elapses and error-corrected by the error detector, and N−K logical pages received from the memory controller,
- wherein K is a positive integer and N is a positive integer greater than K.
Dependencies are inferred from the claim text.