# US 2023/0141385 A1 · Information processing system and information processing system control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0141385 A1 - Document ID: US20230141385A1 - Status: Published application - Kind: A1 - Application number: 17/918,583 - Filed: 2020-06-08 - Published: 2023-05-11 - Earliest claimed: 2020-06-08 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Ryota KITAGAWA; Katsuhisa OGASAWARA - Web page: https://patentgrep.com/patent/US20230141385A1 ## CPC - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/324: by lowering clock frequency - G06F 1/3225: of memory devices - G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/329: by task scheduling - G06F 1/3296: by lowering the supply or operating voltage - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block. ## Claims ### Claim 1 An information processing system comprising: a processor including a power saving mechanism and executing a program loaded into a main memory; and an auxiliary memory storing a program of system basic software that, when executed by the processor, performs the following processes of; holding computational strength data of each execution block constituting an arithmetic application that operates in an operating environment of a computer system including the processor and the main memory in an execution block computational strength data area; holding a roofline model corresponding to an operation frequency and number of cores of the processor and an operation frequency of the main memory in a roofline model data memory; acquiring computational strength data of the each execution block from the execution block computational strength data area; and controlling the operation frequency and the number of cores of the processor and the operation frequency of the main memory based on the roofline model and the computational strength data of the each execution block. ### Claim 2 (depends on 1) The information processing system according to claim 1, wherein the processes include acquiring a current operation frequency and the number of cores of the processor, and a current operation frequency of the main memory. ### Claim 3 (depends on 1) The information processing system according to claim 1, wherein an execution address of the each execution block, the computational strength data of the each execution block, and deadline time of the each execution block indicating time in which processing of the each execution block needs to be ended are held in the execution block computational strength data area. ### Claim 4 (depends on 3) The information processing system according to claim 3, wherein the processes include acquiring the computational strength data of the each execution block and the deadline time of the each execution block from the execution block computational strength data area based on the execution address of the each execution block. ### Claim 5 (depends on 1) The information processing system according to claim 1, wherein the roofline model defines an upper limit value of performance with respect to computational strength for each of combinations of selectable operation frequencies and numbers of cores of the processor and each of selectable operation frequencies of the main memory. ### Claim 6 (depends on 1) The information processing system according to claim 1, wherein the controlling includes: determining the operation frequency and the number of cores of the processor and the operation frequency of the main memory from the roofline model and the computational strength data of the each execution block; measuring execution time of the each execution block; performing the controlling according to the operation frequency and the number of cores of the processor and the operation frequency of the main memory determined; and determining whether or not to perform the controlling based on the overhead time required to perform the controlling. ### Claim 7 (depends on 6) The information processing system according to claim 6, wherein the determining includes: collating the roofline model with the computational strength data of the each execution block; determining which of memory performance of the main memory and arithmetic performance of the processor is a rate-limiting factor in a performance aspect of the arithmetic application; selecting an operation frequency larger than a current operation frequency of the main memory from selectable operation frequencies of the main memory held in the roofline model data memory in a case where the memory performance is determined to be the rate-limiting factor; and selecting an operation frequency and/or number of cores larger than a current operation frequency and/or number of cores from selectable operation frequencies and/or numbers of cores of the processor held in the roofline model data memory in a case where the arithmetic performance is determined to be the rate-limiting factor. ### Claim 8 (depends on 6) The information processing system according to claim 6, wherein whether or not to perform the controlling is determined based on the measured execution time of the each execution block and the overhead time required to perform each predefined control. ### Claim 9 (depends on 6) The information processing system according to claim 6, wherein the operation frequency and the number of cores of the processor and the operation frequency of the main memory are set as the determined operation frequency and the number of cores of the processor and the operation frequency of the main memory in a case where performing the controlling is determined. ### Claim 10 An information processing system control method comprising the steps of: a) holding computational strength data of each execution block constituting an arithmetic application that operates in an operating environment of a computer system including a processor including a power saving mechanism and a main memory; b) acquiring computational strength data of the each execution block; c) storing a roofline model corresponding to an operation frequency and number of cores of the processor and an operation frequency of the main memory; and d) performing control of an operation frequency and number of cores of the processor and an operation frequency of the main memory based on the roofline model and the computational strength data of the each execution block.