Digital loop filter of low latency and low operation and clock data recovery circuit including the same

A digital loop filter comprising:

• a proportional path including a first sigma delta modulation (SDM) arithmetic block circuit;
• and
• an integral path including a second SDM arithmetic block circuit and an integrator, the integral path being configured in parallel with the proportional path,
• wherein the first SDM arithmetic block circuit performs a division operation on an input of the digital loop filter using a first SDM coefficient as a divisor, and
• wherein the second SDM arithmetic block circuit performs a division operation on an output of the first SDM arithmetic block circuit using a second SDM coefficient as a divisor.

A device comprising:

• a receiving circuit;
• and
• a transmitting circuit configured to transmit data to the receiving circuit through a channel,
• wherein the receiving circuit comprises a clock data recovery circuit,
• wherein the clock data recovery circuit includes:
• a bang bang phase detector configured to receive the data and a clock signal and determine whether a phase of the clock signal leads or lags a phase of the data;
• a digital loop filter configured to receive an output from the bang bang phase detector and filter input jitter;
• an accumulator configured to accumulate an output from the digital loop filter;
• an encoder configured to encode an output of the accumulator to generate a phase interpolation code;
• and
• a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code, and
• wherein the digital loop filter comprises:
• a proportional path including a first sigma delta modulation (SDM) arithmetic block circuit;
• and
• an integral path parallel with the proportional path and including a second SDM arithmetic block circuit and an integrator.