Write cache circuit, data write method, and memory

A write cache circuit, comprising:

• a control circuit configured to generate, on the basis of a mask write instruction, a first write pointer and a pointer to be positioned, generate a second write pointer on the basis of a write command, generate a first output pointer on the basis of a mask write shift instruction, and generate a second output pointer on the basis of a write shift instruction;
• wherein, the write command is one of a write instruction and the mask write instruction, and the pointer to be positioned and the second write pointer generated on the basis of the mask write instruction correspond to a same write address;
• a first cache circuit configured to cache data in a queue, cache, on the basis of the first write pointer, the pointer to be positioned, and output a positioned pointer on the basis of the first output pointer;
• wherein, the positioned pointer is the pointer to be positioned that is cached in the first cache circuit, and is configured to instruct a second cache circuit to output the write address written by the second write pointer generated according to the mask write instruction;
• and
• the second cache circuit configured to cache the data in a queue, cache the write address on the basis of the second write pointer, and output the cached write address on the basis of the second output pointer or the positioned pointer.