Epitaxial wafer and semiconductor memory device using the same

An epitaxial wafer, comprising:

• a semiconductor substrate having a front surface and a rear surface opposite to each other;
• a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate;
• and
• a multi-stack on the whole surface of the SRB layer,
• wherein:
• the SRB layer includes a silicon germanium (SiGe) epitaxial layer including a lower layer and an upper layer,
• the lower layer has a concentration gradient of germanium (Ge) therein,
• the upper layer has a uniform concentration of Ge, the uniform concentration being a first concentration of about 2.5 at % to about 18 at %, and
• the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.

A semiconductor memory device, comprising:

• a semiconductor substrate having a front surface and a rear surface opposite to each other;
• a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate, the SRB layer being formed by epitaxially growing silicon germanium (SiGe);
• a plurality of single-crystal silicon (Si) layers on the SRB layer, the plurality of single-crystal Si layers having the same lattice constant as the SRB layer and being arranged at equal intervals;
• a bit line on the front surface of the semiconductor substrate and extending through the plurality of single-crystal Si layers in a vertical direction;
• a transistor body portion including a first source/drain region connected to the bit line, a single-crystal channel layer, and a second source/drain region arranged sequentially in a first horizontal direction;
• a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering an upper surface and a lower surface of the single-crystal channel layer with a gate dielectric layer therebetween;
• and
• a cell capacitor on an opposite side to the bit line from the transistor body portion in the first horizontal direction and including a lower electrode layer connected to the second source/drain region, a capacitor dielectric layer, and an upper electrode layer.