Memory system verification
AssigneeArm Limited
InventorsYuval ELAD, Jason PARKER
Life of this patent
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Abstract
There is provided a data processing apparatus, which is suitable for verifying memory systems. Processing circuitry issues a plurality of memory access requests to a plurality of addresses in a memory. Point-of-trust circuitry receives the memory access requests from the processing circuitry via a first set of intermediate circuits. Secure channel circuitry enables secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry. The point-of-trust circuitry determines whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.
Claims20
A data processing apparatus comprising:
- processing circuitry adapted to issue a plurality of memory access requests to a plurality of addresses in a memory;
- point-of-trust circuitry to receive the memory access requests from the processing circuitry via a first set of intermediate circuits;
- and
- secure channel circuitry to enable secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry, wherein the point-of-trust circuitry is adapted to determine whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.
A data processing method comprising:
- issuing a plurality of memory access requests to a plurality of addresses in a memory;
- receiving the memory access requests from the processing circuitry via a first set of intermediate circuits at point-of-trust circuitry;
- enabling secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry;
- and
- determining whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.
A data processing apparatus comprising:
- means for issuing a plurality of memory access requests to a plurality of addresses in a memory;
- means for receiving the memory access requests from the processing circuitry via a first set of intermediate circuits;
- means for enabling secure communication of a correspondence between the plurality of addresses from the means for issuing a plurality of memory access requests to the means for receiving the memory access requests;
- and
- means for determining whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.
Dependencies are inferred from the claim text.