Semiconductor Device and Method

A method of forming a nanoFET comprising:

• forming on a substrate a multi-layer stack of alternating layers of first and second semiconductor material;
• patterning the substrate and the multi-layer stack to form fins underlying respective multi-layer nano-structures;
• depositing an insulator material between the respective fins;
• forming a dummy gate stack extending over at least one multi-layer nano-structure;
• depositing an ILD layer over the respective fins and respective multi-layer nano-structures;
• removing the dummy gate stack and leaving in its place a gate recess;
• in a region of the substrate, removing the alternating layers of first semiconductor material and patterning the layers of second semiconductor material to form respective channel regions in the second semiconductor material;
• conformally depositing a gate dielectric layer on sidewalls of the gate recess and walls of the respective channel regions;
• conformally depositing an n-type work function layer on the gate dielectric layer within the gate recess and on respective walls of the respective channel regions;
• conformally depositing an anti-reaction layer on the n-type work function layer in the gate recess and along walls of the respective channel regions;
• etching back upper portions of the anti-reaction layer within the gate recess and etching back upper portions of the n-type work function layer within the gate recess, such that a portion of the anti-reaction layer remains within a lower part of the gate recess and along walls of the respective channel regions, and a portion of n-type work function layer remains within the lower part of the gate recess and along walls of the respective channel regions;
• and
• depositing a second conductive layer to fill the gate recess.

A nanoFET device comprising:

• a fin extending from a semiconductor substrate;
• a stack of channel regions above the fin, respective channel regions separated by a first layer of gate dielectric material on a lower channel region, a first layer of first conductive material on the first layer of gate dielectric material, a first layer of anti-reaction material on the first layer of first conductive material, a fill conductor interspaced between the first layer of anti-reaction material and a second layer of anti-reaction material, the second layer of anti-reaction material being on the fill conductor, a second layer of first conductive material on the second layer of anti-reaction material, and a second layer of gate dielectric material on the second layer of first conductive material;
• and
• a gate contact formed on a topmost channel region, the gate contact comprising a third layer of the gate dielectric material, a third layer of the first conductive material, a third layer of the anti-reaction material, and the fill conductor.