Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

A memory device, comprising:

• a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
• an upper substrate, and
• a memory cell array on the upper substrate and including a first memory block;
• and
• a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
• a lower substrate, and
• an address decoder on the lower substrate and configured to control the memory cell array,
• wherein the first memory block includes
• a first core region including first memory cells, and
• a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,
• wherein the first extension region includes
• a plurality of step zones having a step shape in a cross-sectional view, and
• at least one flat zone having a flat shape in the cross-sectional view,
• wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
• wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
• wherein a quantity of step zones in the first extension region is greater than a quantity of flat zones in the first extension region.

A method of manufacturing a memory device including a first semiconductor layer and a second semiconductor layer that are stacked in a third direction perpendicular to first and second directions crossing each other, the method comprising:

• forming the second semiconductor layer that includes a lower substrate and an address decoder on the lower substrate, the address decoder configured to control a memory cell array;
• and
• forming the first semiconductor layer stacked on the second semiconductor layer in the third direction, the first semiconductor layer including an upper substrate and the memory cell array on the upper substrate, the memory cell array including a plurality of memory blocks extending sequentially in a serial pattern, a plurality of wordlines extending in a first direction, and a plurality of bitlines extending in a second direction crossing the first direction,
• wherein each memory block of the plurality of memory blocks includes
• a core region including a plurality of memory cells,
• a first extension region formed adjacent to a first side of the core region, and
• a second extension region formed adjacent to a second side of the core region opposite the first side,
• wherein forming the first semiconductor layer includes
• forming a mold structure based on repeatedly stacking insulating interlayers and sacrificial layers on the upper substrate alternately along the third direction,
• forming the first extension region and the second extension region based on partially removing the mold structure,
• forming wordline cut regions, the wordline cut regions being formed along a boundary of the core region and a boundary of the first extension region, the wordline cut regions being formed to cross an inner portion of the core region and an inner portion of the first extension region, the wordline cut regions being not formed in the second extension region,
• removing the sacrificial layers in the core region and in the first extension region using the wordline cut regions to form one or more spaces,
• forming a plurality of wordlines in the one or more spaces,
• forming a plurality of wordline contacts configured to establish an electrical connection with the plurality of wordlines in the first extension region,
• forming a plurality of through-hole vias in the second extension region, and
• electrically connecting the plurality of wordline contacts with separate, respective through-hole vias of the plurality of through-hole vias,
• wherein the second extension region includes
• a plurality of step zones having a step shape in a cross-sectional view, and
• at least one flat zone having a flat shape in the cross-sectional view,
• wherein the plurality of through-hole vias are formed in the at least one flat zone, and
• wherein the plurality of wordlines and the address decoder are electrically connected with each other by at least the plurality of through-hole vias.