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US 2023/0140958 A1Published application
Methods and Devices to Improve Switching Time by Bypassing Gate Resistor
AssigneepSemi Corporation
InventorsPayman Shanjani, Eric S. Shapiro
Life of this patent
Estimating the term…
Abstract
Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.
Claims16
(canceled)
A switching circuit comprising:
- an input terminal;
- a series arrangement of main FET switches,
- main gate resistors connected to corresponding gate terminals of the main FET switches, the main gate resistors being tied to one another at a main gate resistors common node;
- a common bypass switch block comprising:
- a series arrangement of NMOS FETs having a first NMOS FET and a second NMOS FET, the first NMOS FET being the closest to the input terminal and the second NMOS FET being the closest to the main gate resistors common node;
- a series arrangement of PMOS FETs having a first PMOS FET and a second PMOS FET, the first PMOS FET being the closest to the input terminal and the second PMOS FET being the closest to the main gate resistors common node;
- wherein:
- drain and source terminals of the NMOS FETs are coupled with corresponding drain and source terminals of the PMOS FETs respectively;
- the drain terminals of the first NMOS FET and first PMOS FET are connected together at the input terminal, and
- the source terminals of the first NMOS FET and first PMOS FET are connected together at the main gate resistors common node.
7 more elements
Dependencies are inferred from the claim text.