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US 2023/0086090 A1Published application
Methods and Apparatus for Quotient Digit Recoding in a High-Performance Arithmetic Unit
AssigneeHuawei Technologies Co., Ltd.
InventorMichael Thomas Dibrino
Life of this patent
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Abstract
A divider includes a digit recoder that recodes upper bits of a partial remainder into sets of lower-radix multiples without carry propagate addition. Elimination of the carry propagate adder makes computation of the quotient carry free and independent of the number of bits computed per cycle, thereby enabling a higher number of bits per cycle, as well as increased clock speeds.
Claims32
A redundant binary signed digit (RBSD) divider, comprising:
- a first operand prescaling unit configured to:
- scale a divisor by a first scaling factor;
- a scaled divisor selection unit operatively coupled to the first operand prescaling unit, the scaled divisor selection unit configured to:
- receive an output of the first operand prescaling unit, and selectively swap multiples of plus and minus vectors of inputs to the scaled divisor selection unit to produce selected multiples of a scaled divisor in accordance with a predicted sign of a partial remainder;
- a digit recoder operatively coupled to a plurality of multiplexers, the digit recoder configured to:
- recode at least one N-bit portion of the partial remainder as a combination of two N/2-bit vectors;
- and
- a plurality of full adder stages having inputs operatively coupled to the scaled divisor selection unit and outputs operatively coupled to the plurality of multiplexers, the plurality of full adder stages configured to:
- compress a difference of the partial remainder and the selected multiples of the scaled divisor, the outputs of the plurality of full adder stages being in a redundant format.
6 more elements
A method implemented by a redundant binary signed digit (RBSD) divider, the method comprising:
- prescaling, by the RBSD divider, a divisor and a dividend, the divisor and the dividend being inputs to the RBSD divider;
- and
- iteratively generating, by the RBSD divider, a quotient and a remainder in accordance with the divisor and the dividend utilizing a recoding of one or more radix 2N multiples of most significant bits of a partial remainder.
A system comprising:
- a non-transitory memory storage comprising instructions and data;
- one or more processors in communication with the non-transitory memory storage, wherein the one or more processors execute the instructions;
- and
- an arithmetic unit in communication with the one or more processors and the non-transitory memory storage, the arithmetic unit comprising:
- a first operand prescaling unit configured to:
- scale a divisor by a first scaling factor;
- a scaled divisor selection unit operatively coupled to the first operand prescaling unit, the scaled divisor selection unit configured to:
- receive an output of the first operand prescaling unit, and selectively swap multiples of plus and minus vectors of inputs to the scaled divisor selection unit to produce selected multiples of a scaled divisor in accordance with a predicted sign of a partial remainder;
- a digit recoder operatively coupled to a plurality of multiplexers, the digit recoder configured to:
- recode at least one N-bit portion of the partial remainder as a combination of two N/2-bit vectors;
- and
- a plurality of full adder stages operatively having inputs coupled to the scaled divisor selection unit and outputs operatively coupled to the plurality of multiplexers, the plurality of full adder stages configured to:
- compress a difference of the partial remainder and the selected multiples of the scaled divisor, the outputs of the plurality of full adder stages being in a redundant format.
10 more elements
Dependencies are inferred from the claim text.